xaoc-devices-poczdam

XAOC Devices Poczdam

The Leibniz Binary Subsystem

10 HP Eurorack module

A Leibniz binary-data router for manually or remotely switching two sources, modifying individual data bits, and reclocking data from its voltage-controlled oscillator or an external clock.

Features

  • Routes Leibniz data.
  • Reclocks Leibniz data.
  • Includes a voltage-controlled clock generator up to 2 MHz.

Controls & Jacks (25)

  • Source Select— Illuminated manual button that toggles between the two Leibniz data sources; its illumination indicates the selected source.
  • Clock Output— Outputs the onboard voltage-controlled clock generator.
  • Rate— Sets the manual frequency offset of the onboard voltage-controlled clock generator.
  • Incoming Data Bit 5 Output— 5 V gate output representing bit 5 of the currently selected incoming Leibniz data source.
  • Incoming Data Bit 6 Output— 5 V gate output representing bit 6 of the currently selected incoming Leibniz data source.
  • Outgoing Clock Input— External clock input for the outgoing Leibniz data stream; otherwise it is normalled to the selected source clock.
  • Outgoing Data Bit 5 Input— Input for bit 5 sent to the outgoing Leibniz data header; unpatched it is low, or follows its matching incoming bit when Link is active.
  • Outgoing Data Bit 2 Input— Input for bit 2 sent to the outgoing Leibniz data header; unpatched it is low, or follows its matching incoming bit when Link is active.
  • Outgoing Data Bit 0 Input— Input for bit 0 sent to the outgoing Leibniz data header; unpatched it is low, or follows its matching incoming bit when Link is active.
  • Rate CV Input— CV input for the onboard clock-generator frequency.
  • Outgoing Data Bit 3 Input— Input for bit 3 sent to the outgoing Leibniz data header; unpatched it is low, or follows its matching incoming bit when Link is active.
  • Incoming Data Bit 3 Output— 5 V gate output representing bit 3 of the currently selected incoming Leibniz data source.
  • Incoming Data Bit 2 Output— 5 V gate output representing bit 2 of the currently selected incoming Leibniz data source.
  • Incoming Data Bit 4 Output— 5 V gate output representing bit 4 of the currently selected incoming Leibniz data source.
  • Source Select Input— Trigger/gate input that toggles selection between the two Leibniz sources.
  • Outgoing Data Bit 6 Input— Input for bit 6 sent to the outgoing Leibniz data header; unpatched it is low, or follows its matching incoming bit when Link is active.
  • Link— Illuminated button that normalises each unpatched outgoing bit input to the corresponding incoming bit output; patched inputs override the n
  • Incoming Clock Output— Outputs the clock associated with the currently selected Leibniz source.
  • Incoming Data Bit 7 Output— 5 V gate output representing bit 7 of the currently selected incoming Leibniz data source.
  • Outgoing Data Bit 7 Input— Input for bit 7 sent to the outgoing Leibniz data header; unpatched it is low, or follows its matching incoming bit when Link is active.
  • Incoming Data Bit 0 Output— 5 V gate output representing bit 0 of the currently selected incoming Leibniz data source.
  • Outgoing Data Bit 1 Input— Input for bit 1 sent to the outgoing Leibniz data header; unpatched it is low, or follows its matching incoming bit when Link is active.
  • Incoming Data Bit 1 Output— 5 V gate output representing bit 1 of the currently selected incoming Leibniz data source.
  • Outgoing Data Bit 4 Input— Input for bit 4 sent to the outgoing Leibniz data header; unpatched it is low, or follows its matching incoming bit when Link is active.
  • Clock Range— Selects one of three discrete clock generator frequency ranges: 800–15,000 Hz (middle), 7–120 kHz (lower), or 0.1–2 MHz (upper).

How-To Guides

  • Clock outgoing data from the local generator

Explore the interactive Poczdam panel on BleepDex — tap any control to learn what it does.

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